Field of the Disclosure
The present disclosure relates generally to parasitic capacitance extraction for integrated circuit (IC) designs and, more particularly, to parasitic capacitance extraction for IC designs to be fabricated using multiple patterning.
Description of the Related Art
Dual patterning (or more generally, multiple patterning) often is used during integrated circuit (IC) fabrication to form metal features in closer proximity than is possible in a single mask fabrication process. In a multiple patterning process, different metal features of the same metal layer are formed using different masks during a lithography process. However, misalignment issues and other issues can introduce a significant margin of error, and thus the spacing between a metal feature formed via one mask and a proximate metal feature formed via another mask may vary significantly relative to the designed or intended distance, particularly in contrast to the relatively small margin of error that may be present between metal features formed from the same mask.
This relatively large margin of error in feature spacing introduced by multiple patterning often has pernicious effects in characterizing the IC circuit design. To illustrate, a parasitic capacitance extraction process often is performed on an IC design to estimate the parasitic capacitance likely to be present between two metal features (which is inversely proportional to the spacing between the two metal features). The parasitic capacitance results in turn are used in timing analysis of the circuit, and thus are used to characterize the timing parameters of the IC design. Because of the large variability in relative spacing between two metal features on different masks, the parasitic capacitance extraction process often implements a pessimistic worst-case scenario by assuming that two metal features on separate masks have the minimum spacing reflected by the margin of error, and thus in turn results in the calculation of significantly more conservative timing parameters than may be necessary. The negative impact on timing parameter calculation under this pessimistic assumption often is further exacerbated because the IC designers are not informed as to which metal features are to be assigned to which masks by the IC fabricator, and thus the IC designers typically assume that all proximate metal features are on different masks and thus assume the pessimistic worst-case scenario for all metal feature pairs during the parasitic capacitance extraction and timing analysis processes.